1. Field of the Invention
The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of manufacturing devices comprising conductive nano-dots, and various semiconductor devices comprising same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., memory devices, application specific integrated circuits (ASICs), and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of various features of the integrated circuit devices, e.g., transistors, word lines, etc. Thus, there is a constant drive to reduce the size, or scale, of the features of a typical memory device to increase the overall speed and capabilities of the memory device, as well as electronic devices incorporating such memory devices.
Scaling of various features of integrated circuit devices, e.g., memory devices, has advanced at a very rapid pace in recent years. In fact, critical dimensions of some features on such devices is approaching or exceeding the capability of deep-UV photolithography systems used in forming such features. Moreover, as device dimensions continue to shrink, some performance capabilities may be reduced. For example, extreme scaling of a floating gate on a traditional memory device may result in a floating gate structure that cannot store or maintain sufficient electrical charge such that the memory device may not operate as intended or at least not as efficiently.
Thus, device manufacturers are constantly exploring and developing new techniques to enable highly scaled devices to perform their intended function. As a specific example, it has been suggested that gate structures for a memory device contain a plurality of isolated silicon nano-dots surrounded by an insulating material to thereby improve the charge storage capability of such a structure as compared to a solid layer of polysilicon.
The present invention is directed to various methods and devices that may solve, or at least reduce, some or all of the aforementioned problems.